Design Confidence, Complexity, and Scaling: The Present and Future of System Validation
Abstract
Traditional SoC design-flows are under existential threat in the Post-Moore era: extracted VLSI standard-cell libraries can take months to simulate at advanced process nodes; however, validation of primitive cells is not equivalent to the validation of an exascale computing system or a 20 gigadevice chip. High-order component-level behaviors including various modes of coupling and physical phenomena like hot-carrier injection threaten to play increasing roles in system dynamics, and are inherently difficult to simulate. How do we build confidence without chip-scale physical simulation? This talk analyzes the fundamental assumptions at the heart of the hierarchy- and abstraction-based design paradigm, proposes new methodologies for validating and testing designs both pre- and post-silicon, and interrogates the possibility of validating an infinite-transistor SoC.
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