DE-LOC: Debugging Under Limited Observation and Control

Abstract

In the modern mixed-signal SoC design cycle, designers are frequently tasked with detecting and diagnosing behavioral discrepancies between design descriptions given at different levels of hierarchy, e.g. behavioral vs. transistor level descriptions or behavioral/transistor level descriptions vs. fabricated silicon. One problem is detection, to determine if behavioral differences between design descriptions exist. If such differences (anomalies) are detected, then diagnosis is concerned with identifying the module in a hierarchical design description of the system that is most likely the root cause of the anomaly (typically under the constraint that only the primary outputs of the top-level hierarchies are observed. Previously proposed machine-learning classifiers require prior knowledge about the kinds of likely design errors typically encountered. In this work, we present a novel technique for the algorithmic foundation of circuit diagnosis predictions which does not require any assumptions about the nature of design errors. Our method employs iterative and alternate on-the-fly test generation and least-squares fitting of embedded low-order nonlinear filters to produce a best-guess estimate of the root cause of the anomaly. Experiments are conducted on two test vehicles, an RF transceiver and a phase-locked loop, several bug models are implemented, and the system’s diagnosis predictions are analyzed.

Date
Nov 16, 2016
Event
International Test Conference
Location
Fort Worth, TX
Assistant Professor of Electrical and Computer Engineering in the Department of Electrical and Computer Engineering at the University of Mississippi

My research interests include high-level analog synthesis, nonlinear network dynamics, and design verifiability.