Technology scaling along with unprecedented levels of device integration has led to increasing numbers of analog/mixed-signal/RF design bugs escaping into silicon. Such bugs are manifested under specific system-on-chip (SoC) operating conditions and …
The test generation problem for analog/RF circuits has been largely intractable due to the fact that repetitive circuit simulation for test stimulus optimization is extremely time-consuming. As a consequence, it is difficult, if not impossible, to …
Prior research has established that dynamically trading-off the performance of the RF front-end for reduced power consumption across changing channel conditions, using a feedback control system that modulates circuit and algorithmic level "tuning …
As RF design scales to the 28nm technology node and beyond, pre-silicon simulation and verification of complex mixed-signal/RF SoCs is becoming intractable due to the difficulties associated with simulating diverse electrical effects and design bugs. …
With trends in mixed-signal systems-on-chip indicating increasingly extreme scaling of device dimensions and higher levels of integration, the tasks of both design and device validation is becoming increasingly complex. Post-silicon validation of …
Post-silicon validation of RF/mixed-signal circuits is challenging due to the need to excite all possible operational modes of the DUT in order to establish equivalence between its specified and observed behaviors and to ensure that the DUT does not …
Due to the use of scaled technologies, high levels of integration and high speeds of today's mixed-signal SoCs, the problem of validating correct operation of the SoC under electrical bugs and that of debugging yield loss due to unmodeled …