Mathematical model

TRAP: Test Generation Driven Classification of Analog/RF ICs Using Adaptive Probabilistic Clustering Algorithm

In production testing of analog/RF ICs, application of standard specification-based tests for IC classification is not always an attractive option due to the high costs and test times involved. In this paper, a new test generation algorithm for IC …

Challenge Engineering and Design of Analog Push Pull Amplifier Based Physically Unclonable Function for Hardware Security

In the recent past, Physically Unclonable Functions (PUFs) have been proposed as a way of implementing security in modern ICs. PUFs are hardware designs that exploit the randomness in silicon manufacturing processes to create IC-specific signatures …

Atomic Model Learning: A Machine Learning Paradigm for Post Silicon Debug of RF/Analog Circuits

As RF design scales to the 28nm technology node and beyond, pre-silicon simulation and verification of complex mixed-signal/RF SoCs is becoming intractable due to the difficulties associated with simulating diverse electrical effects and design bugs. …

RAVAGE: Post-Silicon Validation of Mixed Signal Systems Using Genetic Stimulus Evolution and Model Tuning

With trends in mixed-signal systems-on-chip indicating increasingly extreme scaling of device dimensions and higher levels of integration, the tasks of both design and device validation is becoming increasingly complex. Post-silicon validation of …

VAST: Post-Silicon VAlidation and Diagnosis of RF/Mixed-Signal Circuits Using Signature Tests

Post-silicon validation of RF/mixed-signal circuits is challenging due to the need to excite all possible operational modes of the DUT in order to establish equivalence between its specified and observed behaviors and to ensure that the DUT does not …